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本栏目的实验需在 WinXp 上操作。建议在 Virtual Box 虚机上安装WinXp系统,使用更方便。

 MAXII学习板首页
 安装QuartusII6.0软件
 Quartus II 使用入门
 安装ModelSim6.0SE
 使用ModelSim仿真
 使用ModelSim做后仿真
 闪灯程序
 流水灯程序
 数码管计数程序
 计时秒表程序
 PWM控制LED灯亮度程序
 UART通信程序
 PS2口通信程序
 VGA信号发生器程序
 为单片机扩展UART
 相关软件与文档


MAXII CPLD 实验板

数码管计数程序


注:

本实验是针对 MC570/MC240 实验板 设计的,如选用其它开发板实现,部分内容需做调整。

使用实验板上的数码管做十六进制计数,每一秒钟加1。

1.

点击 这里 下载示例工程。*.qar 是 QuartusII 的压缩文档,用 QuartusII6.0 打开。

程序代码如下:

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;

ENTITY maxii_dig IS
  PORT(
    clk     : IN STD_LOGIC;
    seg     : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    sel     : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
  );
END maxii_dig;

ARCHITECTURE maxii_dig OF maxii_dig IS

  COMPONENT digdrv
    PORT(
      clk   : IN STD_LOGIC;
      dig   : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
      seg   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
      sel   : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
    );
  END COMPONENT;

  TYPE TAB_TYPE IS ARRAY(0 TO 15) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
  CONSTANT TAB : TAB_TYPE := (("00111111"),
                              ("00000110"),
                              ("01011011"),
                              ("01001111"),
                              ("01100110"),
                              ("01101101"),
                              ("01111101"),
                              ("00100111"),
                              ("01111111"),
                              ("01101111"),
                              ("01110111"),
                              ("01111100"),
                              ("00111001"),
                              ("01011110"),
                              ("01111001"),
                              ("01110001")); 


  SIGNAL reg : INTEGER RANGE 0 TO 255 :=0;
  SIGNAL dig : STD_LOGIC_VECTOR(15 DOWNTO 0);

BEGIN

  u1 : digdrv
  PORT MAP(
    clk => clk,
    dig => dig,
    seg => seg,
    sel => sel   
  );

  dig <= TAB(reg/16)&TAB(reg MOD 16);

  PROCESS(clk)
    VARIABLE cnt : INTEGER RANGE 0 TO 50000000 := 0;
  BEGIN
    IF clk'EVENT AND clk='1' THEN
      cnt := cnt+1;
      IF cnt=50000000 THEN
        cnt := 0;
        IF reg=255 THEN
          reg <= 0;
        ELSE
          reg <= reg+1;
        END IF;
      END IF;
    END IF;
  END PROCESS;

END maxii_dig;

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY digdrv IS
  PORT(
    clk   : IN STD_LOGIC;
    dig   : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
    seg   : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
    sel   : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
  );
END digdrv;

ARCHITECTURE digdrv OF digdrv IS
  SIGNAL cnt : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN

  PROCESS(clk)
  BEGIN
    IF clk'EVENT AND clk='1' THEN
      cnt <= cnt + 1;
    END IF;
  END PROCESS;

  PROCESS(cnt)
  BEGIN
    CASE cnt(15 DOWNTO 12) IS
      WHEN "0000" => sel <= "00";
      WHEN "0001" => sel <= "01";
      WHEN "0010" => sel <= "01";
      WHEN "0011" => sel <= "01";
      WHEN "0100" => sel <= "01";
      WHEN "0101" => sel <= "01";
      WHEN "0110" => sel <= "01";
      WHEN "0111" => sel <= "00";
      WHEN "1000" => sel <= "00";
      WHEN "1001" => sel <= "10";
      WHEN "1010" => sel <= "10";
      WHEN "1011" => sel <= "10";
      WHEN "1100" => sel <= "10";
      WHEN "1101" => sel <= "10";
      WHEN "1110" => sel <= "10";
      WHEN "1111" => sel <= "00";
    END CASE; 
  END PROCESS;

  WITH cnt(15) SELECT
    seg <= dig(7 DOWNTO 0)  WHEN '0',
           dig(15 DOWNTO 8) WHEN '1'; 

END digdrv;
          




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