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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
ENTITY maxii_pwm IS
PORT(
clk : IN STD_LOGIC;
s0 : IN STD_LOGIC;
s1 : IN STD_LOGIC;
seg : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
leddrv : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END maxii_pwm;
ARCHITECTURE maxii_pwm OF maxii_pwm IS
COMPONENT digdrv
PORT(
clk : IN STD_LOGIC;
dig : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
seg : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END COMPONENT;
SIGNAL click : STD_LOGIC;
SIGNAL dig : STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL regCmp : INTEGER RANGE 0 TO 255 :=0;
SIGNAL regCnt : INTEGER RANGE 0 TO 255 :=0;
SIGNAL pwmOut : STD_LOGIC;
TYPE TAB_TYPE IS ARRAY(0 TO 15) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
CONSTANT TAB : TAB_TYPE := (("00111111"),
("00000110"),
("01011011"),
("01001111"),
("01100110"),
("01101101"),
("01111101"),
("00100111"),
("01111111"),
("01101111"),
("01110111"),
("01111100"),
("00111001"),
("01011110"),
("01111001"),
("01110001"));
BEGIN
u1:digdrv
PORT MAP(
clk => clk,
dig => dig,
seg => seg,
sel => sel
);
PROCESS(clk)
VARIABLE cnt : INTEGER RANGE 0 TO 4999999 :=0;
BEGIN
IF clk'EVENT AND clk='1' THEN
IF cnt=4999999 THEN
cnt := 0;
click <= '1';
ELSE
cnt := cnt+1;
click <= '0';
END IF;
END IF;
END PROCESS;
PROCESS(clk)
BEGIN
IF clk'EVENT AND clk='1' THEN
IF click='1' THEN
IF s0='1' THEN
regCmp <= regCmp+1;
ELSIF s1='1' THEN
regCmp <= regCmp-1;
ELSE
regCmp <= regCmp;
END IF;
END IF;
END IF;
END PROCESS;
PROCESS(clk)
BEGIN
IF clk'EVENT AND clk='1' THEN
regCnt <= regCnt+1;
END IF;
END PROCESS;
pwmOut <= '1' WHEN regCnt <= regCmp ELSE
'0';
leddrv <= pwmOut&pwmOut&pwmOut&pwmOut&pwmOut&pwmOut&pwmOut&pwmOut;
dig <= TAB(regCmp/16)&TAB(regCmp MOD 16);
END maxii_pwm;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY digdrv IS
PORT(
clk : IN STD_LOGIC;
dig : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
seg : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
);
END digdrv;
ARCHITECTURE digdrv OF digdrv IS
SIGNAL cnt : STD_LOGIC_VECTOR(15 DOWNTO 0);
BEGIN
PROCESS(clk)
BEGIN
IF clk'EVENT AND clk='1' THEN
cnt <= cnt + 1;
END IF;
END PROCESS;
PROCESS(cnt)
BEGIN
CASE cnt(15 DOWNTO 12) IS
WHEN "0000" => sel <= "00";
WHEN "0001" => sel <= "01";
WHEN "0010" => sel <= "01";
WHEN "0011" => sel <= "01";
WHEN "0100" => sel <= "01";
WHEN "0101" => sel <= "01";
WHEN "0110" => sel <= "01";
WHEN "0111" => sel <= "00";
WHEN "1000" => sel <= "00";
WHEN "1001" => sel <= "10";
WHEN "1010" => sel <= "10";
WHEN "1011" => sel <= "10";
WHEN "1100" => sel <= "10";
WHEN "1101" => sel <= "10";
WHEN "1110" => sel <= "10";
WHEN "1111" => sel <= "00";
END CASE;
END PROCESS;
WITH cnt(15) SELECT
seg <= dig(7 DOWNTO 0) WHEN '0',
dig(15 DOWNTO 8) WHEN '1';
END digdrv;
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